![]() ![]() The IP-core used as a DMA engine and PCIe block was the Xilinx DMA for PCIe also known as XDMA. The Xilinx PCI Express DMA Drivers provided here Unfortunately, the Xilinx AXI DMA driver doesn't probe properly during the boot and leads to a kernel panic. I want to establish dma transaction of 4K size frames between Jetson & FPGA using the Xilinx DMA engine running on the FPGA. I will rephrase my main question: is this PCIe DMA IP compatible with the Zynq 7000 (FPGA side) and if so, why can I. It'sPete : I am currently working with the Xilinx XDMA driver (see here for source code: XDMA Source), and am attempting to get it to run (before you ask: I have contacted my technical support point of contact and the Xilinx forum is riddled with people having the same. I compiled then the kernel with the xilinx_dma driver as module. I am currently working with the Xilinx XDMA driver (see here for source code: XDMA Source), and am attempting to get it to run (before you ask: I have contacted my technical support point of contact and the Xilinx forum is. ![]() Multi Channel DMA for PCI Express IP’s control logic reads the queue descriptors and executes them.
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